1. Field of the Invention
This invention relates genially to methods of manufacturing integrated circuits in which X-rays expose a wafer through a mask. More particularly, the invention relates to an exposure mask and a method of making the exposure mask in which alignment marks are etched into the exposure mask substrate to allow alignment of the circuit pattern relative to X-ray transparent windows on the mask.
2. Description of Related Art
Exposure masks are used in lithographic techniques during the manufacture of integrated circuits to define circuit features on a wafer. During construction of the mask, a pattern of the circuit features to be exposed onto the wafer is formed on the mask substrate. The pattern of circuit features is made of an absorptive or opaque material which blocks the beam used in the lithographic process. The beam in the lithographic system exposes a suitable sensitized film covering the wafer. When the wafer is exposed, the pattern on the mask is reproduced in the sensitized film. Subsequent processing, such as developing the sensitized film, etching, etc., in accordance with the particular lithographic technique being used reproduces the circuit pattern on the mask on the surface of the wafer to define the desired circuit elements.
In optical photolithographic fabrication techniques, the construction of the mask is accomplished by forming the circuit pattern at any convenient position on a blank mask substrate. In such systems the initial mask substrate is a featureless photographic film and there is no "alignment" necessary between the circuit pattern and the film. Regardless of where the circuit pattern is positioned on the film, it can be aligned with the previously constructed circuit elements on the wafer by moving the mask.
Usually, in addition to the circuit pattern on the mask substrate, one or more mask-to-wafer alignment marks are formed on the mask which have a known position relative to the circuit features in the pattern. The mask-to-wafer alignment marks are used to align the mask with corresponding marks on the wafer prior to the exposure process. Variations in where the circuit pattern is positioned relative to the edges of the mask substrate are compensated for during this mask-to-wafer alignment process.
The tendency of integrated circuits in semiconductor technology, however, is towards ever decreasing structure dimensions in order to increase the density of the circuits and their switching speed. Optical photolithography, which is still used today in the majority of cases, is approaching the limits dictated by the physical resolution of optical systems. Structures having conductive lines less than 0.25 .mu.m in width cannot be made with optical systems. The most promising methods for the production of such fine structures are X-ray beam processes which employ X-ray masks.
Unlike the mask substrate in optical techniques, however, the X-ray mask substrate, upon which the circuit pattern is formed, is not featureless when the circuit pattern is formed on it. Generally, the X-ray mask substrate is a silicon substrate, thick enough to be opaque to X-rays, that has been etched from the back side in certain defined areas to produce mask windows that are X-ray transparent. The mask windows usually formed prior to placing the circuit pattern include a pattern window over which the circuit pattern must be located and one or more mask-to-wafer alignment mark windows to hold corresponding mask-to-wafer alignment marks. The circuit pattern is formed of an X-ray absorptive material, and must be positioned on the mask substrate within the perimeter of its mask windows to ensure that X-rays will pass through the mask substrate to create the corresponding circuit pattern on the wafer.
Accordingly, in the manufacture of X-ray exposure masks, there is an alignment step, not required in optical mask construction, of aligning the circuit pattern and the mask-to-wafer alignment marks relative to their corresponding mask windows on the mask substrate. If the circuit pattern is not positioned within its pattern window, the wafer may not be properly exposed with the entirety of the circuit pattern.
Generally, it would not be too difficult to ensure that the chip pattern is simply located within the confines of its pattern window, provided that the window is made large enough. However, one wants to keep the multiple chips on the wafer close together to improve yield, so increasing the window size is undesirable. Moreover, the circuit pattern on the mask is usually surrounded by a frame that is nearly the same size as the perimeter of the pattern window and which must accurately be positioned directly over the etched sidewalls of the pattern window.
When the mask windows are etched into the mask substrate, the etching process produces angled sidewalls relative to the back side of the substrate. If X-rays are permitted to reach the corners and angled surfaces at the edges of the pattern window, they may be scattered into the central chip exposure area below the circuit pattern on the wafer being manufactured. These X-rays would interfere with the circuit being constructed on the wafer. Accordingly, the frame of X-ray absorptive material referred to above is placed around the circuit pattern on the first or front surface of the mask substrate directly over the perimeter of the pattern window.
The frame cleanly defines the edge of the pattern window and prevents X-rays from scattering into the chip exposure area. This frame must be accurately positioned above the mask window side wall at the exact perimeter of the mask window. This makes accurate alignment of the pattern relative to the mask substrate very important.
In addition to the circuit pattern frame, a molybdenum mask is usually attached below the X-ray mask during exposure. The molybdenum mask has openings corresponding to the mask windows in the exposure mask. If the previously mentioned circuit frame on the front surface is accurately placed during X-ray mask fabrication, it relaxes the requirements on the molybdenum mask placement.
Similar alignment requirements during mask construction are found in connection with the mask-to-wafer alignment mark windows. Some X-ray masks are fabricated with an etched-through opening for the mask-to-wafer alignment mark windows. A polyamide film is placed across these windows to support the mask-to-wafer alignment marks. This allows optical transparency for these windows. If the area of a mask-to-wafer alignment mark window is large, the mask-to-wafer alignment mark on the polyamide film may shift relative to the surrounding silicon mask substrate. The smaller the window and the smaller the area of the unsupported polyamide film, the less the shift and the better alignment between mask and wafer that can be achieved. A small alignment mark window, however, increases the accuracy requirement for placing each mask-to-wafer alignment mark over its corresponding mask-to-wafer alignment mark window.
For all these reasons it is desirable to place the patterns of the exposure mask very accurately with respect to the mask windows in the substrate when the mask is made. Heretofore, there have been no good methods to achieve this first stage of alignment during construction of the mask.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an X-ray mask exposure mask allowing easy alignment of circuit patterns and mask-to-wafer alignment marks relative to windows on the exposure mask.
It is another object of the present invention to provide an exposure mask with alignment marks at precise locations relative to windows on the exposure mask which can be located with an electron beam lithography system.
A further object of the invention is to provide an exposure mask that can be made easily by etching alignment marks at the same time and from the same side as mask windows are etched.